1. Field of the Invention
This invention relates to a method of manufacturing a mask type Read Only Memory (ROM) and more particularly to a writing method in which the time for writing data into the ROM is short.
2. Description of the Prior Art
A prior art mask type Read Only Memory is shown in FIGS. 1 to 3. A gate insulating film 12 and a gate electrode 14 are formed on a P type semiconductor substrate 10. An N.sup.+ region 16 is formed between gate electrodes 14 by a diffusion process. In the Read Only MEMORY shown in FIGS. 1 and 2, MOS transistors Q.sub.11, Q.sub.21 and Q.sub.31 and MOS transistors Q.sub.12, Q.sub.22 and Q.sub.32 are connected in series, respectively. (Load transistors are not shown.)
The number of gates provided in the semiconductor devices depend on user specification. For example, in order to render the MOS transistor Q.sub.22 nonoperative, the source and drain of the MOS transistor Q.sub.22 are shorted by means of an ion implanted layer 18. However, the ion implantation process as mentioned is performed at a initial stage of the wafer fabrication process, and this leads to a delay in the appointed date of delivery.
Proposals to cope with this problem are disclosed in U.S. Pat. No. 4,080,718, wherein an impurity is introduced into the channel region by ion implantation in a final fabrication stage, in order to render the MOS transistor into a depletion type.
In the final step, a PSG layer is etched and the impurity is then introduced into the semiconductor substrate by the ion-implantation process. The semiconductor device fabricated is delivered with the implanted regions exposed. As a result, its reliability is poor.